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/** |
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*** Copyright (C) 1985-1999 Intel Corporation. All rights reserved. |
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*** |
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*** The information and source code contained herein is the exclusive |
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*** property of Intel Corporation and may not be disclosed, examined |
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*** or reproduced in whole or in part without explicit written authorization |
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*** from the company. |
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*** |
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**/ |
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/* |
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* xmmintrin.h |
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* |
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* Principal header file for Streaming SIMD Extensions intrinsics |
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* |
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* The intrinsics package can be used in 2 ways, based whether or not |
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* _MM_FUNCTIONALITY is defined; if it is, the C/x87 implementation |
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* will be used (the "faux intrinsics"). |
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* |
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* |
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* Note that the m128 datatype provided using _MM2_FUNCTIONALITY mode is |
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* implemented as struct, will not be 128b aligned, will be passed |
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* via the stack, etc. MM_FUNCTIONALITY mode is not intended for |
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* performance, just semantics. |
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* |
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*/ |
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#pragma once |
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#ifndef __midl |
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#ifndef _INCLUDED_MM2 |
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#define _INCLUDED_MM2 |
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#include <crtdefs.h> |
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#if defined(_M_CEE_PURE) |
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#error ERROR: XMM intrinsics not supported in the pure mode! |
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#else |
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/* |
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* the m64 type is required for the integer Streaming SIMD Extensions intrinsics |
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*/ |
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#ifndef _MMINTRIN_H_INCLUDED |
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#include <mmintrin.h> |
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#endif |
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#ifdef _MM2_FUNCTIONALITY |
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/* support old notation */ |
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#ifndef _MM_FUNCTIONALITY |
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#define _MM_FUNCTIONALITY |
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#endif |
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#endif |
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#ifdef __ICL |
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#ifdef _MM_FUNCTIONALITY |
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#include "xmm_func.h" |
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#else |
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/* using real intrinsics */ |
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typedef long long __m128; |
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#endif |
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#else |
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typedef union __declspec(intrin_type) _CRT_ALIGN(16) __m128 { |
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float m128_f32[4]; |
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unsigned __int64 m128_u64[2]; |
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__int8 m128_i8[16]; |
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__int16 m128_i16[8]; |
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__int32 m128_i32[4]; |
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__int64 m128_i64[2]; |
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unsigned __int8 m128_u8[16]; |
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unsigned __int16 m128_u16[8]; |
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unsigned __int32 m128_u32[4]; |
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} __m128; |
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#ifndef _INC_MALLOC |
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/* pick up _mm_malloc() and _mm_free() */ |
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#include <malloc.h> |
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#endif |
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#endif |
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/*******************************************************/ |
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/* MACRO for shuffle parameter for _mm_shuffle_ps(). */ |
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/* Argument fp3 is a digit[0123] that represents the fp*/ |
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/* from argument "b" of mm_shuffle_ps that will be */ |
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/* placed in fp3 of result. fp2 is the same for fp2 in */ |
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/* result. fp1 is a digit[0123] that represents the fp */ |
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/* from argument "a" of mm_shuffle_ps that will be */ |
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/* places in fp1 of result. fp0 is the same for fp0 of */ |
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/* result */ |
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/*******************************************************/ |
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#define _MM_SHUFFLE(fp3,fp2,fp1,fp0) (((fp3) << 6) | ((fp2) << 4) | \ |
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((fp1) << 2) | ((fp0))) |
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/*******************************************************/ |
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/* MACRO for performing the transpose of a 4x4 matrix */ |
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/* of single precision floating point values. */ |
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/* Arguments row0, row1, row2, and row3 are __m128 */ |
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/* values whose elements form the corresponding rows */ |
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/* of a 4x4 matrix. The matrix transpose is returned */ |
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/* in arguments row0, row1, row2, and row3 where row0 */ |
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/* now holds column 0 of the original matrix, row1 now */ |
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/* holds column 1 of the original matrix, etc. */ |
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/*******************************************************/ |
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#define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) { \ |
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__m128 tmp3, tmp2, tmp1, tmp0; \ |
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\ |
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tmp0 = _mm_shuffle_ps((row0), (row1), 0x44); \ |
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tmp2 = _mm_shuffle_ps((row0), (row1), 0xEE); \ |
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tmp1 = _mm_shuffle_ps((row2), (row3), 0x44); \ |
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tmp3 = _mm_shuffle_ps((row2), (row3), 0xEE); \ |
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\ |
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(row0) = _mm_shuffle_ps(tmp0, tmp1, 0x88); \ |
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(row1) = _mm_shuffle_ps(tmp0, tmp1, 0xDD); \ |
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(row2) = _mm_shuffle_ps(tmp2, tmp3, 0x88); \ |
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(row3) = _mm_shuffle_ps(tmp2, tmp3, 0xDD); \ |
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} |
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/* constants for use with _mm_prefetch */ |
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#define _MM_HINT_T0 1 |
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#define _MM_HINT_T1 2 |
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#define _MM_HINT_T2 3 |
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#define _MM_HINT_NTA 0 |
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/* (this declspec not supported with 0.A or 0.B) */ |
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#define _MM_ALIGN16 _CRT_ALIGN(16) |
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/* MACRO functions for setting and reading the MXCSR */ |
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#define _MM_EXCEPT_MASK 0x003f |
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#define _MM_EXCEPT_INVALID 0x0001 |
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#define _MM_EXCEPT_DENORM 0x0002 |
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#define _MM_EXCEPT_DIV_ZERO 0x0004 |
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#define _MM_EXCEPT_OVERFLOW 0x0008 |
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#define _MM_EXCEPT_UNDERFLOW 0x0010 |
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#define _MM_EXCEPT_INEXACT 0x0020 |
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#define _MM_MASK_MASK 0x1f80 |
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#define _MM_MASK_INVALID 0x0080 |
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#define _MM_MASK_DENORM 0x0100 |
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#define _MM_MASK_DIV_ZERO 0x0200 |
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#define _MM_MASK_OVERFLOW 0x0400 |
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#define _MM_MASK_UNDERFLOW 0x0800 |
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#define _MM_MASK_INEXACT 0x1000 |
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#define _MM_ROUND_MASK 0x6000 |
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#define _MM_ROUND_NEAREST 0x0000 |
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#define _MM_ROUND_DOWN 0x2000 |
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#define _MM_ROUND_UP 0x4000 |
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#define _MM_ROUND_TOWARD_ZERO 0x6000 |
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#define _MM_FLUSH_ZERO_MASK 0x8000 |
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#define _MM_FLUSH_ZERO_ON 0x8000 |
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#define _MM_FLUSH_ZERO_OFF 0x0000 |
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#define _MM_SET_EXCEPTION_STATE(mask) \ |
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_mm_setcsr((_mm_getcsr() & ~_MM_EXCEPT_MASK) | (mask)) |
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#define _MM_GET_EXCEPTION_STATE() \ |
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(_mm_getcsr() & _MM_EXCEPT_MASK) |
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#define _MM_SET_EXCEPTION_MASK(mask) \ |
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_mm_setcsr((_mm_getcsr() & ~_MM_MASK_MASK) | (mask)) |
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#define _MM_GET_EXCEPTION_MASK() \ |
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(_mm_getcsr() & _MM_MASK_MASK) |
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#define _MM_SET_ROUNDING_MODE(mode) \ |
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_mm_setcsr((_mm_getcsr() & ~_MM_ROUND_MASK) | (mode)) |
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#define _MM_GET_ROUNDING_MODE() \ |
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(_mm_getcsr() & _MM_ROUND_MASK) |
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#define _MM_SET_FLUSH_ZERO_MODE(mode) \ |
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_mm_setcsr((_mm_getcsr() & ~_MM_FLUSH_ZERO_MASK) | (mode)) |
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#define _MM_GET_FLUSH_ZERO_MODE(mode) \ |
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(_mm_getcsr() & _MM_FLUSH_ZERO_MASK) |
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/* IN : __m64 a */ |
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/* OUT : none */ |
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/* RETURN : __m128 : (float)a */ |
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/******************************************************/ |
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__inline __m128 _mm_cvtpu8_ps(__m64 a) |
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{ |
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return _mm_cvtpu16_ps(_mm_unpacklo_pi8(a, _mm_setzero_si64())); |
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} |
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/******************************************************/ |
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/* NAME : _mm_cvtps_pi8 */ |
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/* DESCRIPTION : Convert 4 single-precision float */ |
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/* values to 4 8-bit integer values */ |
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/* IN : __m128 a */ |
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/* OUT : none */ |
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/* RETURN : __m64 : (char)a */ |
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/******************************************************/ |
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__inline __m64 _mm_cvtps_pi8(__m128 a) |
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{ |
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return _mm_packs_pi16(_mm_cvtps_pi16(a), _mm_setzero_si64()); |
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} |
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/******************************************************/ |
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/* NAME : _mm_cvtpi32x2_ps */ |
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/* DESCRIPTION : Convert 4 32-bit integer values */ |
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/* to 4 single-precision float values */ |
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/* IN : __m64 a : operand 1 */ |
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/* __m64 b : operand 2 */ |
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/* OUT : none */ |
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/* RETURN : __m128 : (float)a,(float)b */ |
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/******************************************************/ |
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__inline __m128 _mm_cvtpi32x2_ps(__m64 a, __m64 b) |
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{ |
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return _mm_movelh_ps(_mm_cvt_pi2ps(_mm_setzero_ps(), a), |
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_mm_cvt_pi2ps(_mm_setzero_ps(), b)); |
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} |
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#if defined __cplusplus |
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}; /* End "C" */ |
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#endif /* __cplusplus */ |
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#endif /* defined(_M_CEE_PURE) */ |
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#endif |
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#endif |
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